1. Field of the Invention
The present invention relates to a semiconductor integrated circuits in which it is hard to cause a breakdown and leakage current to breakdown, of an oxide film of a bipolar transistor and an MOS transistor due to the formation of interconnections (including one having a spiral inductor and a pad) electrically connected to the bipolar transistor and the MOS transistor by patterning through plasma etching and, and a process for manufacturing the, semiconductor integrated circuit.
2. Description of the Prior Art
Progress in high integration of semiconductor integrated circuits has been made in recent years. With high integration, the distance between the base and emitter of a bipolar transistor that constitutes a semiconductor integrated circuit, has been reduced. In a bipolar transistor employed in a high-frequency circuit, for example, the distance between the base and emitter has been reduced to increase cut-off frequency. With its high integration as well, a gate oxide film of a MOS transistor that constitutes a semiconductor integrated circuit, has been reduced in thickness.
With a view toward implementing the high integration of such a semiconductor integrated circuit, plasma etching is used in a process for manufacturing bipolar and MOS transistors.
The term plasma etching means a method of etching using ions and atoms in a plasma produced by a glow discharge in a reactive gas. In this case, the state of the plasma depends on etching conditions such as the type of reactive gas, etc. The etching using the ions in the plasma is performed as follows: Electrons in the plasma, which have been produced by a glow discharge of a reactive gas between negative and positive electrodes, are allowed to rapidly reach both electrodes to thereby produce a negative potential between the two electrodes. Thereafter, ions in the plasma are accelerated under the negative potential to impact on a wafer.
Incidentally, the density of the plasma results in nonuniformity on the wafer surface due to the nonuniformity of the plasma upon plasma etching, whereby the wafer is locally charged within the wafer surface. Upon patterning by plasma etching, electrical charges are borne between upper and lower portions of a pattern due to overetching.
The above-described plasma etching has been used in the conventional manufacturing process of the semiconductor integrated circuit.
In a bipolar transistor of a DPSA (Double Poly-Si Self-Aligned) structure shown in FIG. 15, which is employed in a high-frequency circuit, for example, the thickness of an insulating oxide film 146 located between a base electrode 138 and an emitter electrode 142 is set to a range of 0.1 .mu.m to 0.2 .mu.m to reduce the distance between the base electrode 138 and the emitter electrode 142. Therefore, when an interconnection 103 electrically connected to the base electrode 138 is formed by patterning through plasma etching, the interconnection 103 is charged by ions and electrons resultant from a plasma, so that a current flows between the base electrode 138 and the emitter electrode 142 through the insulating oxide film 146 located between the two electrodes. As a result, a problem arose in that a breakdown of the insulating oxide film 146 located between the base electrode 138 and the emitter electrode 142 due to plasma etching and a leakage current flowing between the base electrode 138 and the emitter electrode 142 incident to its breakdown would occur in the post-manufacture bipolar transistor. The manner in which the current flows between the base electrode 138 and the emitter electrode 142 through the insulating oxide film 146 located between the two electrodes, is shown in FIG. 15 by the arrow indicated by a broken line.
Similarly, in a MOS transistor shown in FIG. 16, which responds to high integration, for example, the thickness of a gate oxide film 151 is set to about 1500 nm. Therefore, when an interconnection 103 electrically connected to a gate electrode 152 is formed by patterning through plasma etching, the interconnection 103 is charged by ions and electrons resultant from a plasma, so that a current flows between the gate electrode 152 and a substrate 131 through the gate oxide film 151. As a result, a problem arose in that a breakdown of the gate oxide film 151 due to plasma etching and a leakage current flowing between the gate electrode 152 and the substrate 131 incident to its breakdown would occur in the post-manufacture MOS transistor. The manner in which the current flows between the gate electrode 152 and the substrate 131 through the gate oxide film 151, is shown in FIG. 16 by the arrow indicated by a broken line.